期刊文献+

分布算术的并行计算技术研究 被引量:3

Research and Design of Parallel Architecture of Distributed Arithmetic
下载PDF
导出
摘要 针对在FIR、DCT、FDWT等的实现中广泛应用的分布算术计算方法进行了深入的分析,对当前分布算术实现方法中存在的性能和实现代价等方面的缺点进行了归纳和总结.针对SIMD二维阵列计算结构这样的体系结构模型,对分布算术的计算并行性进行分析,寻找出分布算术计算中所隐含的计算并行性,从而使得能够应用于二维SIMD阵列来进行高效的计算. This paper deeply analyzes the distributed arithmetic using in the implementations of FIR,DCT and FDWT etc.,and summarizes the performance and cost disadvantages of current technologies.Aimed at the architecture of the 2-D SIMD processing element array,this paper searches the potential computing parallelism,which is suitable for computing on the 2-D SIMD processing element array.
出处 《微电子学与计算机》 CSCD 北大核心 2009年第5期25-28,共4页 Microelectronics & Computer
关键词 分布算术 并行DA PE阵列 前缀求和 distributed arithmetic PDA PE array prefix-accumulation
  • 相关文献

参考文献8

  • 1Keshab K Parhi. VLSI digital signal processing systems design and implementation[ M ]. New York: John Wiley & Sons, 1999.
  • 2Sasao T, Iguchi Y, Suzuki T,et al. On LUT cascade realizations of FIR filters[ C] // Proceedings of the 8th Euromicro Conference on Digital System Design. Japan, 2005: 467 - 474.
  • 3Lau D, Schneider A, Ercegovac M D, et al. A FPGA- based library for online signal[J]. VLSI Signal, 2001, 28(1/2): 129- 143.
  • 4Grover R S, Shang W, Li Q. A faster distributed arithmetic architecture for FPGAs [ C]// Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field -programmable gate arrays. California, 2002:31 -39.
  • 5Motra A S, Bora P K, Chakrabarti I. An efficient hardware implementation of DWT and IDWT[C]//The proceedings of the 2003 Conference on Convergent Technologies for Asia - Pacific Region. India: Guwahati, 2003:95 - 99.
  • 6HiUis W D, Steele G L, Jr. Data parallel algorithms[J]. Communications of the ACM, 1986,29(12). 1170 - 1183.
  • 7El Rewini H, Abd El Barr M. Advanced computer architecture and parallel[M]. USA. John Wiley & Sons,2005.
  • 8向淑兰,曹良帅.数字信号处理器中阵列乘法器的研究与实现[J].微电子学与计算机,2005,22(10):133-136. 被引量:5

二级参考文献5

  • 1A D Booth. A Signed Binary Multiplication Technique,Quarterly Journal of Mechanics and Applied Mathematics,1951, 236-240.
  • 2C S Wallace. A Suggestion for a Fast Multiplier. IEEE trans. On Electronic Computers, 1964, EC-13:14-17.
  • 3R Katti. A Modified Booth Algorithm for High Radix Fixed-Point Multiplication. IEEE trans, on very large scale integration systems, 1994, 2(4): 522-524.
  • 4许琪.[D].西安微电子研究所,2000.
  • 5A Kaviani, S Brown. Efficient Implementation of Array Multipliers in FPGAs. 1998.

共引文献4

同被引文献16

  • 1卢丽君,廖明生,张路.分布式并行计算技术在遥感数据处理中的应用[J].测绘信息与工程,2005,30(3):1-3. 被引量:20
  • 2RICHARDSON I E G.视频编解码器的设计-开发图像与视频压缩系统[M].北京:国防科技大学出版社,2005.
  • 3CHEN W H. A fast computational algorithm for the discrete cosine transforms [J]. IEEE Transactions on Communications, 1977,25(9): 1004-1009.
  • 4Ahera. Avalon Interface Specifications [DB/OL].2009-11.
  • 5李文敬,黄容伟,廖伟志.基于相对梯度的自适应图像分形压缩并行算法[J].微电子学与计算机,2007,24(10):115-117. 被引量:3
  • 6周一鸣,张超,张曾科.基于局部方差和DCT变换的混合分形图像编码算法[J].计算机科学,2007,34(10):241-243. 被引量:3
  • 7Barnsley M F. Fractal everywhere [M]. New York: Academic Press, 1988.
  • 8Jacquin A E. Image coding based on a fractal theory of contractive lmage transformation [J]. IEEE TrarL Im- age Processing. 1992, 1(1): 18-30.
  • 9Fisher Y. Fractal image compression: theory and ap- plication [M]. berlin: Springer Verlag , 1995.
  • 10Dake Liu. Embedded DSP processor design: applica- tion specific instruction set processors [M]. Morgan Kaufmann: [s. n. ], 2008.

引证文献3

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部