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基于Cache Missing的RSA计时攻击 被引量:4

Timing Attack against RSA on Cache Missing
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摘要 由于同步多线程允许多个执行线程之间共享处理器的执行单元,为共享Cache存储器提供了线程间一个实现简单、高带宽的隐通道,使得一个恶意线程能够监视其他线程访问的资源.以OpenSSL0.9.7c实现的RSA算法为攻击对象,通过执行一个间谍线程,监视密码线程,观测RSA解密时读取Cache数据变化时反应的时间特性,通过分析这些时间信息推论出RSA的解密密钥.最后介绍了如何减轻甚至消除这种攻击的建议. Simultaneous multithreading enables multiple execution threads to share the execution resources of a superscalar,the shared access to memory caches provides an easily used high bandwidth covert channel between threads,allowing that a malicious thread can monitor the execution of another thread.This paper targets at RSA cryptosystem implemented via OpenSSL0.9.7c,monitores the cryptographic thread by executing a Spy thread,recording the timing characteristic during the RSA decryption when reading the Cache.The attacker can recovers the original key by analyzing these timing measurement.Finally,we provide some suggestions of how this attack could be mitigated or eliminated entirely.
机构地区 军械工程学院
出处 《微电子学与计算机》 CSCD 北大核心 2009年第5期180-182,186,共4页 Microelectronics & Computer
基金 国家自然科学基金项目(60772082) 军械工程学院科学研究基金项目(YJJXM07033) 河北省自然科学基金数学研究专项(08M010)
关键词 RSA 同步多线程 CACHE 滑动窗口 RSA simultaneous multithreading Cache sliding windows
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参考文献5

  • 1Kocher P. Timing attacks on implementations of dieellman, RSA, DSS and other systems [ C]// Crypto 1996, Springer, Lecture Notes in Computer Science 1109. Heidelberg, 1996:104 - 113.
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  • 5邓高明,张鹏,陈开颜,赵强.Cache在旁路攻击中的理论应用及其仿真实现[J].微电子学与计算机,2007,24(5):76-79. 被引量:5

二级参考文献3

  • 1谢满德.嵌入式CPU设计中Cache性能的全局优化[J].微电子学与计算机,2005,22(2):143-147. 被引量:3
  • 2Daniel Page.Theoretical use of cache memory as a cryptanalytic side-channel[EB/OL].URL:http://eprint.iacr.org/2002/169/
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