10位100MHz采样保持电路设计

DESIGN OF A 10 bit,100 MHz SAMPLE-HOLD CIRCUIT

设计了一种适用于10位100MHz的流水线模数转换器的采样保持电路.利用SMIC0.13μmCMOS工艺,设计了一个直流增益为87.6dB的全差分自举增益放大器,其功耗仅7.2mW,且达到0.05%精度的响应时间小于4ns.在采样时钟频率为100MHz,输入信号频率为10MHz时,该采样保持电路的无杂散动态范围(SFDR)为80.7dB.

A sampling-hold circuit at 10 bit and 100 MHz pipelined ADC is presented. A differential gainboosted amplifier is designed with a high gain of 87.6 dB under SMIC 0. 1μm CMOS process, a power consumption of 7.2 mW, and settling time to 0.05% accuracy of 〈4 ns. For a 10 MHz sine wave under 100 MHz sampling clock, the sampling-hold circuit achieves a SFDR of 80. 7 dB.