可扩展的低成本双域模乘模除器算法及其VLSI实现

New Algorithms and Architecture for a Scalable Low-cost Dual-fields Modular Multiplier/Divider

本文通过应用Booth编码技术和多比特移位技术,有效地改进了有限域模乘模除算法,不仅使素域模乘的运算速度提高了一倍,而且使素域模除运算所需的迭代次数减小了40%.在算法改良的基础上,本文提出一种可配置的有限域模乘模除器结构,实现了模乘与模除运算,及素域与多项式域算术的硬件复用,大幅度地降低了硬件成本.另外,本文提出的硬件结构使用以字为单位的运算单元,采用流水线结构,具有良好的扩展性.因此,本文的模乘模除器具有灵活性、安全性和低成本的综合优势,可以广泛应用于各种高性能、低成本的便携移动设备,为各种无线终端设备用户提供高性能的信息安全服务.

A novel architecture, which combines both multiplier and divider, is presented in this paper. Based on the techniques of radix-4 booth encoding and multiple bits shifting, the Multiplication and Division algorithms in GF（P） are greatly improved： multiplication speed is doubled and iteration time of division is reduced by 40%. Scalable hardware architecture is also proposed for the combined multiplier and divider, which employs word level processing element and pipeline architecture. This architecture can execute two functions of multiplication and division with very low cost and relatively high performance. So it will be widely used in mobile equipment, providing information security service for the users of wireless terminals.