基于SS序列集成电路布线技术

The VLSI Floor Floorplan Design based on SS

集成电路（IC）是在半导体基片上形成的完整的电子线路。当前芯片里的电路与系统日趋复杂，超大规模集成电路（VLSI）设计技术水平也在逐渐提高。VLSI设计中一般采用分级设计的方法。布图设计过程是整个VLSI分级设计中非常关键的步骤之一。基于Single-Sequence的集成电路布图就是在SS编解码的应用下对芯片中各单元的摆放进行优化从而达到芯片面积利用率最大化。本文重点介绍了在SS序列生成版图后各单元间连线的设计以及如何根据水平／垂直约束图提取版图中各单元的坐标。并根据要连模块的位置关系对其连线经过的模块进行有条件加线宽的处理。

The integrated circuit （IC） is integrated electronic circuit produced on a silicon wafer. The circuits and systems on chip become more and more complex and the VLSI design technology is also improved quickly. The hierarchical design is widely used in VLSI design. The floorplan design is to make a floorplan from the circuit components description and the net-hsts. The VLSI multi-floor＇s floorplan design based on Single-Sequence is a technology used to design a better idea to put the module so that the chip can get a smaller area. This article focuses on the SS in the sequence generated map of the unit after the connection between the design and how the level / vertical constraint graph extraction in the territory of the unit.