利用Cadence设计COMS低噪声放大器

CMOS LNA Design Using Cadence

结合一个2.4 GHz CMOS低噪声放大器(LNA)电路,介绍如何利用Cadence软件系列中的IC 5.1.41完成CMOS低噪声放大器设计。首先给出CMOS低噪声放大器设计的电路参数计算方法,然后结合计算结果,利用Cadence软件进行电路的原理图仿真,并完成了电路版图设计以及后仿真。仿真结果表明,电路的输入/输出均得到较好的匹配。由于寄生参数,使得电路的噪声性能有约3 dB的降低。对利用Cadence软件完成CMOS射频集成电路设计,特别是低噪声放大器设计有较好的参考价值。

With an example of 2.4 GHz CMOS Low Noise Amplifier （LNA） ,it is introduced that how to design the CMOS LNA using IC 5.1.41 of Cadence. First,example includes calculation of circuit parameters. And then, with the help of this calculation results,the Schematic simulation,circuit layout and the postlayout simulation are completed. The simulation results show that the input and output networks matched well, but the noise performance decreased 3 dB because of the parasitic parameters. It is useful to the design of CMOS RF IC using Cadence,especially the CMOS LNA design.