基于FPGA的多功能数字钟设计

Design of Multifunctional Digital Clock Based on FPGA

本文介绍了利用EDA技术自顶向下的设计方法,提出了一个多功能数字钟的设计方案,采用VerlogHDL语言设计了数字钟系统的各个模块,在QuartusII开发平台下进行了编译、仿真、下载,实现了基本计时显示和设置、调整时间、闹钟和秒表功能。

This thesis describes the top-down method in EDA technology, presents a design scheme of a multi-functional digital clock. The modules of the system are designed by Verlog HDL, and are compiled, simulated and downloaded in Quartus II. The functions of time display and setup, time adjustment, alarm clock, and stopwatch are implemented.