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显影关键点及其对精细线路制作的影响 被引量:2

The Critical Point of Developing and It's Impact on Fine Line's Manufacture
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摘要 文章结合过显侵蚀干膜的原理,试验设计不同的显影条件,分析干膜线路和蚀刻线路的情况,确定显影关键点及其对精细线路制作的影响。 This article based on the theory of over-development attacking the exposed dry film,designs a series of experiments with different developing parameter, through the analysis of the circumstance of developed dry film line and etched line,confirms the critical factor of development and it's influence on fine line's facture.
作者 田玲 李志东
出处 《印制电路信息》 2009年第5期30-33,共4页 Printed Circuit Information
关键词 显影 显影(像)点 干膜 精细线路 development break point dry film fine line
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参考文献1

  • 1Karl H.Dietz. Dry film photoresist processing technology. electrochemical publications LTD,2001.

同被引文献17

  • 1林金堵;梁志立;陈培良.现在印制电路先进技术[M]上海:中国印制电路行业协会,201247-55.
  • 2小林;蔡积庆;龚永林.积层印制电路板[M]上海:中国印制电路行业协会,200335-41.
  • 3JALONEN P,TUOMINEN A. The applicability of electrodeposited photo resists in producing ultra-fine lines using sputtered seeding layers[J].{H}CIRCUIT WORLD,2002,(2):11-13.
  • 4田玲;李志东.蚀刻喷淋压力对精细线路制作的影响[A]深圳,2008.
  • 5SHIMIZU K,KOMATSU K,TANAKA Y. Controlled surface etching process for fine line/space circuits[A].USA:IEEE,2002.
  • 6WATANABE R,KIM H W. New circuit formation technology for high density PWB[A].USA:Curran Associates Inc,2005.
  • 7WATANABE R. Samsung's big idea[J].Circuitree,2005,(7):12-16.
  • 8KOBAYASHI K. Fabrication of fine line patterns for advanced build-up package[J].Int Conf Electron Packg,2001,(4):393-398.
  • 9YUNG K C,YUE T M,CHART K C. The effects of pulse plating parameters on copper plating distribution of micro via in PCB manufacture[J].IEEE Trans Electron Packg Manuf,2003,(2):106-109.
  • 10CHESKIS H P,CHEN S F,BRENNEMAN W L. Ultra thin copper foil for HDI applications[J].Circuitree,2004,(11):10-19.

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