基于FPGA的数据采集系统的设计

Design of a Data Acquisition System Based on FPGA

介绍了以FPGA为核心控制模块的数据采集系统。设计中采用自上而下的方法,将FP-GA分为几个模块,并论述各模块的功能和设计方法。FPGA模块采用VHDL语言进行仿真。整个系统可以实现8路最大工作频率为5MHz语音信号的采集。

This paper introduces the high-speed data acquisition system based on FPGA, the core logic control module of the system. In the design, top-down method is used and FPGA is divided into some function modules. The system can acquire 8-route analog signals with 5 MHz of maximal frequency.