基于FPGA的三相锁相环的优化设计方案

Optimized implementation scheme of three phase phase-locked loop based on FPGA

提出了一种基于可编程逻辑门阵列(FPGA)的适用于电力系统的三相锁相环(PLL)的优化设计与实现方案。首先介绍了包括鉴相器、环路滤波器和压控振荡器等在内的锁相环基本结构和工作原理,然后利用模块化的设计方法利用VHDL语言设计了这些模块。为了尽量节省逻辑资源,在利用FPGA实现该锁相环的过程中,采用了面积共享的优化设计方案;同时提出了一种新的正弦函数产生方法,该方法将CORDIC算法和查表法相结合,这样既保证了数值的精度,又提高了运算速度。该锁相环在Altera公司Cyclone EP1C12Q240C8芯片上得到了验证。验证结果表明,最终优化设计后的三相锁相环大大减少了逻辑资源的使用量,能够很好地跟踪系统频率的变化并锁住基波相位。

An optimized implementation scheme of FPGA based digital three phase phase-locked loop which fits in electric power system is presented in this paper. At first, this paper introduces basic architecture and principle of this phase-locked loop including phase discriminator, loop filter and voltage controlled oscillator （VCO）, etc. Then this design of phase-locked loop is optimized in order to save the logic source of FPGA by optimization scheme of sharing space. A new method, which is combined with CORDIC algorithm and look-up table is proposed to generate sine function. This method could increase computing speed and guarantee the accuracy of results at the same time. At last, this design is implemented on ALTERA＇s FPGA Cyclone EP1C12Q240CS. The results verify that this system could reduce the usage of logic resource of FPGA and track the variation of frequency and lock the base phase well.