摘要
利用分布式算法对FIR滤波器的硬件实现进行了探讨,在数乘累加的理论上,对分布式算法的串行、并行和拆分查找表法的FPGA硬件实现方法进行了研究。结合FPGA查找表结构,兼顾资源及运行速度的要求,用拆分查找表的方法设计了16阶8位常系数FIR滤波器,并在Quartus Ⅱ 5.0下进行仿真,仿真结果验证了该算法的有效性和实时性。
By meas of Distributed Algorithm（DA）, hardware design of FIR digital filter was discussed. Based on theory of data accu-mulation algorithm, FPGA hardware realization of parallel DA, series DA, and series-parallel DA were studied. By use of speed,resource and series-parallel DA, 16-step constants coefficients high speed FIR filter was designed,and the filter was simulated under the eonditions of QuartuslIS.0.Simulation results showed that the design method has valididity,real time effectiveness and feasibility.
出处
《电子技术应用》
北大核心
2009年第5期32-34,38,共4页
Application of Electronic Technique
基金
河北省自然科学基金资助
关键词
FPGA
分布式算法
拆分查找表
FIR滤波器
FPGA
DA（Distributed Algorithm）
table partitioning to yield a reduced size
FIR filter
