54Mb/s NRZ时钟数据恢复电路的设计与实现

Design and implementation of a 54Mb/s NRZ clock data recovery circuit

提出一种采用双环路的时钟数据恢复电路,电路采用改进型Hogge鉴相器;鉴相环电荷泵充放电电流为13.06μA,改善了输出时钟的抖动影响;压控振荡器采用四级环型振荡结构,由伪差分结构延迟单元组成,降低了系统电路设计难度,减小了VCO的增益。通过Cadence软件的Spectre工具仿真,能够顺利地从54Mb/s的非归零码数据中提取出54MHz的同步时钟,时钟占空比为50%,满足设计要求。

This paper presents a clock date recovery circuit using dual-loop, in which an improved Hogge phase detector is utilized. Both the current of charge and discharge of the charge pump are 13.06 μA, which reduces the clock-jitter of the output. The VCO uses four-ring structure, each delay module is design by the pseudo-differential structure that reduces the difficulty of circuit and the gain of the VCO. Verified with Spectre simulator of Cadence software, it can recovery 54 MHz clock from the 54 Mb/s of the NRZ data. Pulse duration ratio of the clock is 50%, it meets the design requirements.