H.264中自适应二进制算术编码器的FPGA实现

FPGA implementation of adaptive arithmetic coder in H.264

H.264是目前国际上最新、最有前途的视频压缩标准,基于上下文的自适应二进制算术编码是H.264中一种高效的熵编码,但算法比较复杂,执行速度不高。本文提出一种基于流水线的自适应二进制算术编码器的FPGA结构。在实现过程中,对原有的软件流程进行了部分改进以满足硬件实现要求,采用流水线及并行处理技术设计整个电路。

H.264 is the newest and the most promising video compressing standard in the world. The context-based adaptive binary arithmetic coding algorithm, which is based on H.264,is an efficient but complicated and low-speed algorithm. So an FPGA architecture is proposed. The original software flow is improved for the needs of hardware implementation. A pipe-line and parallel technology is applied in the whole circuit, which is implemented in the spartan3 FPGA. The coding speed can reach 1 bit/cycle and the maximal clock frequency can reach 90.4MHz.