期刊文献+

基于verilog-A数控LC振荡器系统的行为级建模

Behavioral Modeling of Digial Controlled LC Oscillator System with Verilog-A Language
下载PDF
导出
摘要 在全数字锁相环中数控振荡器和由∑Δ调制器所构成的系统是一个规模很大的电路,采用传统的电路级描述难以在现有的EDA工具中仿真。为此提出了一种基于Verilog-A语言的行为级建模方法来对系统进行仿真。详细介绍了数控振荡器系统中各模块的建模方法,并给出了各模块建模的关键代码。仿真结果表明对数控振荡器的行为模型不仅能提高仿真效率还能很好模拟实际系统。该行为模型具有较好的实用性,所得结果可用于指导具体电路的设计。 In all-digital-phase-locked loops (ADPLL), the scale of the system composed of digitally controlled oscillator (DCO) and sigma-delta modulator (SDM) is too big to be simulated in traditional circuit level with current EDA tools. Therefore, the method of behavioral modeling of the DCO system based on Verilog-A was presented. A behavioral modeling method of each block in the system was introduced, and the key codes of each block modeling were given. The results show that those models can improve simulating efficiency and simulate the actual system well. Therefore, the behavioral modeling method is practical and can be used to guide the realization of the system.
出处 《半导体技术》 CAS CSCD 北大核心 2009年第4期375-380,共6页 Semiconductor Technology
基金 中国863高科技项目(2007AA01Z2b3) 国家重点基础研究发展项目(2007CB310701)
关键词 数控振荡器 ∑Δ调制器 全数字锁相环 VERILOG-A 关键代码 行为级建模 DCO SDM ADPLL Verilog-A key code behavioral modeling
  • 相关文献

参考文献5

  • 1STASZEWSHI R B, MUMHAMMAD K. All-digital TX frequency synthesizer and discrete time receiver for bluetooth radio in 130-ran CMOS [J]. IEEE J SSC, 2004, 39 (12): 2278-2291.
  • 2Cadence verilog-ams language reference [ K]. Version 5.5.
  • 3KUNDERT K. Predicting the phase noise and jitter of PLL- based frequency synthesizers [ R/OL] . ( 2006 ), http ://www. designs-guide, com.
  • 4RILEY T, COPELAND M. Delta-sigma modulation in fractional-n frequency synthesis [J] .J SSC, 1993,28(5) :553- 559.
  • 5WOOGEUN R. Multi-bit delta-sigma modulation technique for fractional-n frequency synthesizers [ D]. Urbana-Champaign : University of Illinois, 2001.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部