深亚微米混合信号全芯片ESD电路设计

Whole-Chip ESD Protection Design for Deep Submicron Mix-Signal CMOS VLSI

随着CMOS工艺的发展,集成电路元件的尺寸持续减小,芯片的静电放电(ESD)保护设计受到了更大的挑战。从系统的角度出发,采用电压域分别保护后通过隔离器件连接的方法完成了对深亚微米芯片ESD保护系统的设计。设计中分析了传统输出端保护可能存在的问题,并采用稳妥的方法对输出端进行了保护。这种架构提高了整个芯片的抗ESD能力,节省了芯片面积,达到了对整个芯片提供全方位ESD保护的目的。设计采用TSMC0.18μm工艺,测试结果验证了该设计的有效性。

The design of robust ESD circuits remains challenging because ESD failure mechanisms become more acute as critical circuit dimensions continue to shrink. An ESD protection system for deep submicron chips was designed using a systematic view. After every power domain was protected separatel crosscoupled ESD diodes were used to connect the isolated power domain grounds. The problems existed Y, in traditional output ESD protections were analyzed, moreover, an output ESD protection was designed in a safe manner. With smaller area, this structure enhances the whole-chip ESD resistance capability and achieves the design purpose. The prototype test chip is fabricated in a TSMC 0.18 μm CMOS technology, the test result verifies the efficiency of the ESD design.