期刊文献+

动态参数模型确定SoC中异步FIFO深度的方法 被引量:5

New Method for Determining the Depth of Asynchronous FIFO in SoC Based on the Model of Dynamic Parameters
下载PDF
导出
摘要 针对超大规模集成电路和片上系统设计中确定异步FIFO浓度的问题,根据异步FIFO运行时的属性提出FIFO动态参数模型,该模型包括FIFO饱和度、写入端和读出端数据传输率及上溢/下溢频率。在该模型的基础之上,分析异步FIFO的深度与动态参数之间的关系,采用功能仿真方法确定片上系统中异步模块之间数据传输所需FIFO的深度。对典型实例的分析表明,采用这种方法能够在保证系统数据通信性能的前提下,获得最小的FIFO深度,优化系统资源的使用。 Aimmig at determining the depth of asynchronous first-in first-out (FIFO) in very large scale integrated (VLSI) circuits and system on chip (SoC) a model of dynamic parameters based on the running-time attribute of the asynchronous FIFO is presented in this paper. This model contains FIFO saturation, writing reading rate and overflow/underflow rat through the function simulation. On the base of this model, the depth of asynchronous FIFO in system on chip (SoC) can be determined by analyzing the relationship between these dynamic parameters and the depth of FIFO through the function simulation. According to the typical example provided, using the presented method can effectively minimize the depth of FIFO and optimize the usage of resource.
出处 《电子科技大学学报》 EI CAS CSCD 北大核心 2009年第3期447-450,共4页 Journal of University of Electronic Science and Technology of China
关键词 异步FIFO FIFO深度 片上系统 超大规模集成电路 asynchronous FIFO depth of FIFO system on chip VLSI circuits
  • 相关文献

参考文献10

  • 1DALLY W J, POULTON J W. Digital systems engineering [M]. Cambridge, UK: Cambridge University. Press, 1998.
  • 2BALCH M. Complete digital design[M]. New York: McGraw-Hill, 2003.
  • 3APPERSON R W. A dual-clock FIFO for the reliable transfer of high-throughput data between unrelated clock domains[D]. California: UC Davis, 2004.
  • 4鲁玲.多时钟域数据传递的FPGA实现[J].现代电子技术,2007,30(21):130-132. 被引量:6
  • 5陈征.FIFO缓冲存储器的结构及应用[J].汕头大学学报(自然科学版),1998,13(1):85-89. 被引量:10
  • 6COCHRAN A J, BAILEY P N, CARR L S. FIFO buffer depth estimation for asynchronous gapped payloads: United States Patent. US, 7227876B 1 [P]. 2007-06-05.
  • 7RHA Kyoungscok, CHOI Kiyoung. Arca-efficient buffer binding based on a novel two-port FIFO structure[C]// Proceedings of the Ninth International Symposium on Hardware/Software Codesign. Copcnhagcm: ACM, 2001: 122-127.
  • 8宋宇鲲,王锐,胡永华,高明伦.使用排队论模型对FIFO深度的研究[J].仪器仪表学报,2006,27(z3):2485-2487. 被引量:10
  • 9APPERSON R W, YU Z, MEEUWSEN M J, et al. A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains[J]. IEEE Transactions on Very Large Scale Integration (VLS1) Systems, 2007, 15(10): 1125-1134.
  • 10刘祥远,陈书明.一种高性能的异步FIFO结构[J].电子学报,2007,35(11):2098-2104. 被引量:6

二级参考文献25

共引文献25

同被引文献37

引证文献5

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部