可配置的TFT-LCD控制器IP核的设计

Design of IP core in configurable TFT-LCD controller

设计实现了一种基于Avalon总线的,显示分辨率和像素深度均可配置的TFT-LCD控制器IP核。根据自顶向下的设计思想,将IP核进行层次功能划分设计,采用Verilog硬件描述语言实现该控制器以及它的外围逻辑时序的全部功能。并对IP核进行仿真验证,最后加入到Nios Ⅱ系统中,该IP核经测试效果良好。

This paper designs and implements an Avalon bus-based TFT-LCD controller IP core, its display resolution and pixel depth can be configured. This paper uses the mind of top-down to design IP core＇ s level function, and uses Verilog HDL to achieve all the functions of the controller and its peripheral logic timing. This paper simulated and verified this IP core, jointed it to the Nios-II system. The test results proved that this IP core is very well.