MEMS器件用低表面应力SOI材料的制备及应用

Preparation and MEMS application of low surface stress SOI wafer

利用改进的BGSOI工艺成功制备低表面应力的厚膜SOI晶片,并表征晶片的显微结构、界面和表面应力。研究结果显示:晶片的各层区域分明,界面平整,上层硅厚度为76.5μm,SiO2埋层厚度为0.865μm;晶片键合良好,有效键合面积大于95%,键合强度大于13.54 J/m2;表面应力小于12.6 MPa,已成功制作出微加速度计。

Low surface stress thick-film SOI wafers were prepared by modified BGSOI technology. And microstructure, bonded interface and surface stress of thick-film SOI wafer were characterized. The result shows that the bonding interface is clear, and there is no void in the bonding interface. The thickness of top silicon layer and buried oxide layer is 76.5 micrometer and 0.865 micrometer respectively, the virtual bonding area exceeds 95%, bonding strength is more than 13.54 J/m^2, surface stress is lower than 12.6 MPa. A micro-accelerometer has been successfully produced.