基于AMBA总线的AES算法设计

Design of AES Algorithm Based on AMBA

描述了基于AMBA(高级微控制器总线架构)总线的AES(高级加密标准)算法硬件设计。AES算法采用状态机实现,具有4种工作模式、支持2种密钥以及AHB(高级高性能总线)。采用实验室的SEGPS平台对设计进行仿真验证,并与采用C++语言实现的AES进行比对验证。最后,选用FPGA (现场可编程门阵列)进行综合,结果显示,可工作最高频率为140.1 MHz,占用逻辑单元的资源为6 977,数据吞吐率最高为351.65 Mbit/s。

This paper presents a hardware design of AES algorithm based on AMBA. Our design, using the state machine, can configure four modes of AES operation with 128 bit, 192 bit cipher key. Furthermore, the interface between AHB and AES was also designed. Designed functionality was verified on SEGPS platform by comparing our results with the right data which were figured out by C＋＋ program. Finally, through synthesis, using the Stratix Ⅱ ES2S60F1020C4, it can operate up to 140.1 MHz, and uses 6 977 ALUTs. The maximum throughput of our design is 351.65 Mbps.