SoC低功耗设计及其技术实现

Low Power Design and Implementation in SoC

文章根据低功耗设计理论和方法,分别从系统级、模块级及RTL级三个层次上考虑一款SoC芯片功耗设计。在系统级采用工作模式管理方式,在模块级采用软件管理的方式,RTL级采用门控方式,三种方式的应用大大降低芯片了的功耗。仿真分析表明,该芯片的低功耗设计策略取得了预期的效果,实现了较低的动态功耗与很低的静态功耗。该SoC采用0.18μm CMOS工艺库实现,面积为7.8mm×7.8mm,工作频率为80MHz,平均功耗为454.268mW。

A set of SoC low power design methods is presented and used to different level ofA SoC, such as system level, IP module level and RTL level. In system level operating mode is considered, in module level software management is considered and in RTL level gating clock is considered. Power simulation results show that the static and dynamic power of the SoC is quite low. The goals of the low power design methods applied on the design are achieved. The SoC has been implemented in 0.18 μm CMOS process, the area is 7.8 mm × 7.8 mm, the operation frequency is 80 MHz and the power dissipation is about 454.268 mW.