应用于JPEG2000的离散小波变换并行超大规模集成结构

Parallel VLSI architecture of discrete wavelet transform for JPEG2000

针对离散小波变换硬件资源占用率高的问题,提出了一种应用于JPEG2000的离散小波变换并行超大规模集成(VLSI)结构。引入了基于时间差的(9,7)小波并行滤波技术,使行和列滤波器同时进行滤波;采用2×2转置模块,实现了几个寄存器代替大量的中间转置存储空间。实验结果表明,该结构在关键路径的约束条件下,有效降低了硬件复杂性,大大提高了硬件资源利用率,使其几乎达到100%。该结构已通过VHDL布局布线后仿真验证,并可作为单独的IP核应用于正在开发的航行数据记录仪(VDR)雷达图像采集卡中。

In order to solve the problem that the Very Large Scale Integration（VLSI） architecture of a Discrete Wavelet Transform（DWT） wastes a huge amount of hardware resources, a parallel VLSI architecture based on the DWT for JPEG2000 is proposed. The architecture introduces a （9,7） wavelet parallel filtering technique based on the time difference, so that the row processor and the column processor can process the signals in a parallel way. By using a 2 × 2 transforming module, several kinds of registers can be used to substitute a lot of medium transforming memories. Experimental results show that the proposed architecture can efficiently decrease the hardware complexity and can improve hardware utilization to 100 % nearly under the tight critical path. The architecture has been implemented in a post-route VHDL, and can be used as a compact and independent IP core for Voyage Data Recorder （VDR） radar image acquisition cards.