跳频收发系统中的跳频频率合成器设计

Design of Frequency Hopping Synthesizer in Frequency Hopping Transceiver

跳频频率合成器是跳频收发系统设计的核心,也是技术实现的一个难点。提出一种应用DDS和PLL实现高速跳频的频率合成设计方案,并对其硬件进行了详细设计,最后对其所能达到的性能指标进行估算。结果表明,该方案能够满足系统设计的要求,其创新点在于把DDS和PLL的优点有机地结合起来实现了高速跳频,摒弃了用直接数字频率合成DDS输出频率不能太高或用锁相环PLL合成频率锁定时间较长的缺点。

Frequency Hopping（FH） synthesizer is the core of FH transceiver and also a difficulty for the design. In the paper,a project of fast FH synthesizer realized with DDS and PLL is brought forward,and the hardware design is completed. Its performance is estimated, and the results show that the blue print meets the requirements of the system design. The advantages of DDS and PLL are combined to realize high speed FH when designing,the shortcomings for the DDS, which can not outputs higher frequency,and the PLL,whose locking time is longer are abandoned.