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数字超声检测仪中窄带激励脉冲的CPLD实现 被引量:2

Implementation of Narrowband Powering Pulse in Digital Ultrasonic Detector Based on CPLD
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摘要 为了提高数字式超声波检测仪系统的距离分辨率,使超声检测系统具有探测速度快、精度高、分辨率高、可靠性高等优点,要求激励i脉冲的脉宽和频率具有可调性。采用分频器的设计思想,给出了一种频率、脉宽可调的窄脉冲发生器设计原理,并用CPLD实现了一种可满足数字超声波无损检测仪激励信号需要的脉冲信号发生器,通过实验仿真证明所产生的窄带激励脉冲具有频率,脉宽可调的特点,从而提高了系统性能,使参数调整更加方便。同时,还可用于其它需要产生频率,脉宽可变脉冲的场合。 To improve the digital ultrasonic detectors' the distance resolution, make them have the merits of rapid detecting speed, high precision, high resolution and high reliability, it requires that the powering pulse is adjustable. By adopting the design approach of frequency divider,the paper gives the design principle of narrow pulse generator, whose frequency and pulse width are adjustable. And a kind of pulse signal generator, which can satisfy the need of digital ultrasonic detectors' powering signal, is designed by using CPLD. The narrowband powering pulse produced by this method has the merits that its frequency and pulse width are adjustable. Consequently, it enhances the system performance and makes parameter adjusting more easily. Meanwhile, the design method of this paper can be used to produce other pulses with volatile frequencies and widthes.
出处 《计算机仿真》 CSCD 北大核心 2009年第5期337-340,共4页 Computer Simulation
关键词 超声波检测 分频器 复杂可编程逻辑器件 窄脉冲发生器 Ultrasonic detecting Frequency divider Complex programmable logic device ( CPLD ) Narrow pulse generator
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  • 1时昕,王东辉,侯朝焕.深亚微米SoC中的电源/地网络设计[J].微电子学与计算机,2004,21(12):198-202. 被引量:10
  • 2Yu X Y,Do M A,Jia L,et al.Design of a low power wide-band high resolution programmable frequency divider[J].IEEE Transactions on VLSI Systems,2005,13(9):1098~1103
  • 3Ram Sixth Rana.Dual-modulus 127/128 FOM enhanced prescaler design in 0.35μm CMOS technology[J].IEEE Journal of Solid State Circuits,2005,40(8):1662~1670
  • 4Hung C M,K K O.A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop[J].IEEE J.Solid-State Circuits,2002,37(4):521~525
  • 5Tournier E,M Sié,Graffenil J.Hish-speed dual-modulus prescaler architecture for programmable digital frequency dividers[J].IEEE Electronics Letters,22nd November 2001,37(24):1433~1434
  • 6Cicero S Vaucher,Igor Ferencic,et al.A Family of low-power truly modular programmable Dividers in Standard O.35μm CMOS Technology[J].IEEE Journal of Solid-State Circuits,2000,35(7):1039~1045
  • 7David A Hodgesl.Analysis and design of digital integrated circuits in deep submicron technology.北京:电子工业出版社,2005
  • 8Jan M Rabaey,Anantha Chandrakasan.Digital integrated circuits:a design perspective (Second Edition)[M].北京:清华大学出版社,2004

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