具有概率分离计算功能的二级流水线电路设计

Design of a Two-Stage Pipelined Circuit with Probability Splitting Calculation

在通信系统的接收机中,解调器的输出通常是串行的"软比特"信息。利用模拟电路设计的信道译码器需要并行的数据,以实现后验概率译码计算。为了实现串并转换以及降低模拟译码器的复杂度和功耗,利用0.6μm CMOS工艺,为模拟译码器设计了新型的二级流水线结构的输入接口电路。在实现"软比特"信息串并转换的同时,具有概率分离计算功能。模拟结果表明,该电路比传统的设计方法降低了功耗和芯片面积,工作速度可达50MHz,整体功耗为304.8μW。

In the receiver of the communication system, the output of demodulator is usually serial ＂soft-bit＂ information. For channel decoder based on analog circuits, parallel data are needed to realize a-posterior probability calculation. To realize serial-to-parallel conversion and decrease the complexity and power dissipation of the analog decoder, a novel two-stage pipelined input interface circuit for analog decoder was designed based on 0. 6μm CMOS technology. The circuit could not only realize serial-to-parallel conversion of the ＂soft-bit＂ information, but also has the probability splitting calculation function. Simulation results showed that the input circuit reduced power consumption and chip area, compared with circuit designed using conventional method. Operating at 50 MHz, the circuit had a total power dissipation of 304. 8 μW.