可伸缩双域Montgomery乘法器的优化设计与实现

An optimized scalable and unified hardware architecture of Montgomery multiplier

模乘运算是公钥密码算法中的关键运算,本文基于全字运算的Montgomery模乘算法,设计了具有可伸缩硬件结构的模乘器。该模乘器可以基于固定的数据路径宽度对任意长度的数据进行运算,并且能够支持两个有限域上的运算。最后用Verilog硬件描述语言对该乘法器的硬件结构进行代码设计,并用Synopsys公司的Design Complier在Artisan SIMC 0.18μm typical工艺库下综合。实验结果表明,相对于其他模乘器设计,本文设计具有较高的时钟频率,并且由于大大减少了运算所需的时钟周期数,模乘运算速度较快。

Modular multiplication is the core operation of PKC（public key cryptography）. Based on the full-word Montgomery multiplication algorithm, a scalable and unified modular multiplier is proposed, which can work with any precision of the opemnds and work in both prime and binary fields. It is captured in Verilog and synthesized under 0. 18 μm CMOS technology. The result indicates that this work can achieve high clock frequency and perform efficiently than other works, as the clock numbers are reduced greatly.