基于FIFO循环缓冲区的DSP外围设备实时调度研究

Scheduling DSP peripheral devices in real-time based on FIFO circular buffering

使用先入先出(FIFO)循环缓冲区方案解决实时系统中数字信号处理(DSP)外围设备调度问题。解析证明了循环缓冲区可调度的充要条件是外围设备总响应时间占总时间的比率小于1,并对数据帧周期输入到外围设备的情况,提出一种求解开辟缓冲区最小空间的离线数值计算方法。该方法应用于某高端导航接收机DSP外围设备调度设计,可以快速求出缓冲区所需开辟的最小空间。

A scheme based on FIFO circular buffering to schedule DSP peripheral devices in real time sys tems is presented. The circular buffer schedulablity requires the ratio Of the total response time of the peripheral device to total time is less than 1, which is the sufficient and necessary condition. An off line numerical method is proposed to calculate the minimal space of the buffer in the case of data frames inputting periodically into pe ripheral devices. Furtherraore, the scheme can quickly calculate the minimal space of the circular buffer when it is applied to a certain navigation receiver design.