一种小面积的高吞吐率AES协处理器设计

A Small-area Design of High Throughput AES Coprocessor

提出了一种AES协处理器的结构设计,加解密部分采用加解密复用的单个轮函数迭代的无流水线结构,内含的密钥调度电路可进行128、192与256位密钥的动态双向密钥调度.该协处理器可配置在ECB、CBC或CTR工作模式下,工作模式与数据输入输出的处理不影响处理器的数据吞吐率.基于SMIC0.13μm CMOS工艺的综合结果表明,该电路的关键路径延时最短为4.45ns,在206MHz的最高时钟频率下,128位密钥长度下的数据吞吐率可达到2.4Gb/s.电路门数为7.848万门.

This paper presents an architecture design of AES coprocessor, in encryption and decryption part of it, an encryption and decryption multiplexed non-pipelined architecture that uses a round function unit iteratively is used, and a key schedule circuit included can conduct 128, 192 and 256-bit key＇s dynamic bidirectional key schedule. This coprocessor can be configured in ECB, CBC or CTR modes of operation, the processing of modes of operation and data input and output will not affect the data throughput of the coprocessor. The synthesis results based on SMIC 0.13μm CMOS technology shows that the critical path delay is 4.45 ns, it delivers a throughput of 2.4 Gb/s in 128-bit key mode at the highest 206 MHz clock. The gate count is 78 480 gates.