摘要
设计了一个应用于FFT(快速傅里叶变换)系统的43位浮点乘法器.该乘法器采用一种先进的MBA(modified Booth algorithm)编码与部分积产生技术以及一种优良的折中压缩结构,使用了平方根进位选择加法器,同时,还运用了一种方法使得最终求和、舍入和规格化同时完成,提高了运算速度.采用四级流水线,使用FPGA进行验证,采用0.18μm标准单元库综合实现,系统时钟频率可达184.4MHz.
A 43-bit floating-point multiplier that is used in the FFT system is designed in the paper. The multiplier adopts an advanced technology for encoding with modified Booth algorithm and producing the partial products. Also, it uses the square-root carry select adder and adopts a method to make the ultimated addition, rounding and normalizing done simultaneously, thus the speed is improved. With the technology of four-stage pipeline, it is implemented on FPGA. Being synthesized with 0.18μm CMOS standard cell library, the frequency of system can reach 184.4MHz.
出处
《微电子学与计算机》
CSCD
北大核心
2009年第6期17-20,共4页
Microelectronics & Computer
基金
江苏省自然科学基金项目(BK2007026)
