期刊文献+

可配置处理器环境下的异构多核结构的设计与实现

The Design and Implementation of Heterogeneous Multicore Architecture in a Processor-Configurable Environment
下载PDF
导出
摘要 提出了一种针对特定多线程应用程序的异构多核结构设计方案.此方案通过进行指令集扩展,可以方便的构建异构多核结构,而且还兼有同构多核结构的特点.还给出了该结构在Tensilica平台上的实现方案,并且将运行Motion-JPEG程序得到的数据与同构结构下的数据相比较,验证了该设计方案的正确性以及高效性. This paper is to propose a design solution for heterogeneous multi core architecture according to a kind of specific applications. Heterogeneous structure, which also has the merit of homogeneous structure, can be constructed conveniently by instruction extension. Besides, it also shows the implementation of this structure on Tensilica platform, and compares the data gained by running Motion Jpeg on the structure to those gained on homogeneous structure, to validate the eorrecmess and high-effectiveness of our design.
作者 陈劭 付宇卓
出处 《微电子学与计算机》 CSCD 北大核心 2009年第6期162-165,共4页 Microelectronics & Computer
基金 上海市科委基金(06SA16)
关键词 异构多核 指令集扩展 Tensilica多线程 heterogeneous multi-core instruction extension Tensilica multi-thread
  • 相关文献

参考文献7

  • 1Fei Sun, Srivath.s Ravi, Anand Raghunathan. Applicationspecific heterogeneous multiprocessor synthesis using extensible processors [ J ]. IEEE Transactions on CAD of Integrated Circuits and Systems, 2006, 25(9) : 1589- 1602.
  • 2Chris Rowen. Engineering the complex SOC fast flexibel design with configurable processors[M]. USA: Prentice Hall, 2005.
  • 3David Butenhof. Programming with POSIX threads[M]. USA: Addison - Wesley, 2003.
  • 4林明亮,祝永新.基于SimpleScalar的异构多核仿真器[J].微电子学与计算机,2007,24(7):204-208. 被引量:7
  • 5Chen Guobing, Chen Tianzhou, Yan Like. On - chip communication framework design for embedded heterogeneous [D]. Zhejiang: Zhejiang University,2007.
  • 6Seng Lin Shee, Andrea Erdos, Sri Parameswaran. Heterogeneous multiprocessor implementations for JPEG: a case study[J]. CODES ISSS, 2006,11(3) :217-222.
  • 7所光,杨学军.双核处理器性能最优的共享Cache划分[J].微电子学与计算机,2008,25(9):28-30. 被引量:4

二级参考文献12

  • 1贺占庄.一种多处理器并行计算机系统的设计[J].微电子学与计算机,2006,23(2):198-200. 被引量:7
  • 2http://www.simplescalar.com[EB/OL].
  • 3Manjikinn N.Multiprocessor enhancements of the SimpleScalar tool set[J].ACM SIGARCII Computer Architecture News.March 2001,29(1):8-15.
  • 4Boyer F R,Yang Liping,Aboulhamid E M,et al.Multiple SimpleScalar processors,with introspection,under SystemC[C].Circuits and Systems,2003.MWSCAS'03.Proceedings of the 46th IEEE International Midwest Symposium,2003:1400-1404.
  • 5Sinharoy B, KaUa R N, Tendler J M, et al. Power 5 system microarchitecture[J]. IBM J. Res. Dev, 2005, 49 (4/5) : 505 - 521.
  • 6Kongetira P, Kongetira P, Aingaran K, et al. Niagara: a 32- way multithreaded spare processor[J]. Micro IEEE, 2005, 25(2) :21 - 29.
  • 7Stone H S, Turek J, Wolf J L. Optimal partitioning of cache memory[J]. IEEE Trans. Comput, 1992, 41(9) : 1054 - 1068.
  • 8Guang S, Xunjun Y, Guanghui L, et al. IPC-based e.ache partitioning: an IPCoriented dynamic shared cache partitioning mechanism[ C]//International Conference on Convergence and Hybrid Information Technology-ICHIT 2008. Korea, Busan, 2008.
  • 9Suh G E, Rudolph L, Devadas S. Dynamic partitioning of shared cache memory[J]. Supercomput, 2004, 28(1) : 7 - 26.
  • 10Dybdahl H, Stenstr P, Natvig L. A cache - partitioning aware replacement policy for chip multiprocessors[J ]. High Performance Computing- HiPC 2006, 2006(12) :22 - 34.

共引文献9

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部