CCD时序电路与数据缓存器的一体化设计

An integrative design of multi-channel CCD timing generator and data cache

在分析了Sarnoff公司的VCCD512H面阵型CCD图像传感器驱动时序关系的基础上,结合某CCD相机电子系统的总体要求,完成了基于FPGA驱动时序发生器与数据缓存器的一体化设计。选用Xilinx公司的XQ2V3000系列FPGA作为硬件设计平台,运用VHDL语言对驱动时序电路和数据缓存子系统进行了描述,并采用Alter公司的QuartusII集成设计软件对设计进行了RTL级仿真及配置。仿真结果表明,所设计的基于FPGA一体化时序与数据缓存子系统不仅可以满足CCD芯片和视频处理的时序要求,还可以与CCD相机控制系统进行可靠的串行通信,从而检测和控制相机的工作状态。

Based on the analysis of Sarnoff＇s VCCD512H-area CCD image sensor-driven timing relations, combining space-area CCD camera electronic system＇s collectivity request, completed the integrated design of timing-driven generator based on FPGA and data cache. Use Xilinx＇s XQ2V3000 series FPGA as a platform for hardware design. Described the drive timing circuit and data cache subsystem using VHDL, and use Aher＇s Quartus Ⅱ integrated design software to accomplish the RTL-level simulation and configura- tion of the design. The simulation results show that the design of the integration of timing based on FPGA and data cache memory subsystem ,not only meet the CCD chips and the video processing timing requirements, but also keep the reliable serial communica- tions with the CCD camera crew, so as to detect and control the camera＇s working conditions.