不同设计层次下密码运算部件抗功耗攻击能力量化评估技术

Quantitative Evaluation of the Cryptographic Block's Resistibility to Power Analysis Attack at Different Design Level

为设计有效抗功耗攻击且具有高性价比的安全芯片,需要在其设计实现过程中量化分析密码运算部件抗功耗攻击的防护能力,其关键在于评估防护能力以及模拟密码运算部件的瞬态功耗.以成功实施功耗攻击所需的样本数来量化密码运算部件抗功耗攻击能力,提出了成功实施功耗攻击所需样本数的估算方法;在RTL(register transfer level)级、综合后以及布局布线后等不同设计层次进行瞬态功耗模拟的技术;以及以空间换时间和多线程并行模拟技术,以提高瞬态功耗的模拟速度,也可以用于大规模电路的瞬态功耗模拟.

In the design and implementation of cost effective and power-analysis-resistant secure chip, it is necessary to perform quantitative analysis of the cryptographic block＇s ability to prevent power analysis attack. The key of quantitative analysis is to evaluate the resistibility to power analysis attack and simulate the instantaneous power trace. The number of power samples required to perform power analysis attack successfully is used to characterize the resistibility. The number of samples is computed based on the signal-to-noise ratio of the corresponding power analysis attack. In order to compute the number of power samples, it is necessary to simulate the instantaneous power trace of cryptographic blocks. The instantaneous power trace is expressed as a discrete time sequence of instantaneous current, not the average power consumption or the peak power consumption. A method is presented to simulate the cryptographic block＇s instantaneous power trace through the design cycle including RTL（register transfer level） design, synthesis and place ~ route. Two kinds of speedup methods which are the time reduction at the cost of space and the multi-thread parallel simulation are proposed. So that the simulation can be speeded up, and also be applicable to power trace simulation of large scale circuits.