基于VMM的流量管理芯片验证

Verification of Traffic Managing Chip Based on VMM

流量管理芯片的验证是目前业界的热点与难点,验证工程师们一直在努力寻找用于流量测量的较好方法。采用System Verilog语言,基于Synopsys公司最新推出的验证方法学VMM,提出一种用于流量管理芯片验证的分层次验证环境。该环境对流量测量方法进行重点研究,放弃采用参考模型的传统验证思路,提供一种参考基准可变,时间窗位置可移,长度可调的,可在不同设计间高度重用的流量检测机制。该验证环境及验证方法在海思半导体某流量管理芯片开发过程中的成功应用,保证了芯片开发质量,缩短了项目开发周期,为其他同类芯片的开发提供了强有力的支持。

The verification of traffic managing chip is currently the hotspot and difficulty in this field. Verification engineers have been trying their best to find a better way to traffic measurement. Adopting System Verilog,based on VMM library supplied by Synopsys, one layered verification environment is presented. Focusing on the research of traffic measurement, abandoning the traditional verification thought with RM, the environment provides one traffic check mechanism,in which reference benchmark is variable, time window is movable and time length is adjustable. Successful application of the verification environment and methods introduced in this article in traffic managing chip in Hisilicon not only shorten the period and assure the quality but also strongly supportd the development of congeneric chips.