面向SDTA处理单元的一种功耗评估方法

An Efficient Power Estimation Approach for the Synchronous Data Transfer Architecture

本文针对同步数据传输体系结构(SDTA)处理单元提出了一种功耗评估方法。基于处理单元的结构抽象,结合SDTA特点,采取不同方法对各个子部件功耗分别进行评估。该方法不仅满足了精度要求,而且具有较好的灵活性与较高的工作效率,特别适应于专用指令集处理器的设计流程。实验表明,与PrimePower门级功耗评估工具的模拟结果比较,70%与90%的样本误差分别小于8.2%与10.8%,但评估效率提高了12000倍左右。

An efficient power estimation approach is proposed for the processor elements as for the synchronous data transfer architecture. Based on the architecture-level model and its modularity characteristics, different methods are proposed to estimate the power consumption of each sub-component. This approach meets the precision requirement. The advantages of its flexibility and high-efficiency make it suitable for the application-specific instruction processor design process. The experimental results show that 70% and 90% of the estimation errors are below 8. 2% and 10.8% respectively, and then the efficiency increases by 12000 times, compared with the gate-level estimation by PrimePower.