可重构点乘运算的FPGA设计

Reconfigurable Point Multiplication Design Based on FPGA

文章在深入分析ECC点乘运算的FPGA实现的基础上,提出了一种参数可重构的、基于正规基有限域运算的ECC点乘运算结构。该点乘运算结构采用了复用、并行化等措施,在FPGA上实现了GF(2^191)的ECC点乘运算。在Altera FPGA上的仿真结果表明:在50Mhz时钟下,一次点乘运算只需413.28us。

Based on the analysis deep into the implementation of ECC point multiplication on FPGA, we propose a reconfigurable ECC point multiplication architecture which is based on the normal basis in finite field. This architecture utilizes many methods which aim at the characteristics of point multiplication, such as reuse, parallelization, etc., finally implement the ECC point multiplication of GF（2^191） on FPGA platform. The simulation on Altera FPGA indicates that, one point multiplication only takes 413.28 us under 50 Mhz clock frequency.