摘要
A novel device structure with a vertical double-gate and dual-strained channel is presented.The electrical characteristics of this device with a gate length of 100 nm are simulated.With a Ge content of 20%,the drain currents of the strained-Si NMOSFET and the strained-SiGe PMOSFET compared to the universal SOI MOSFETs are enhanced by 26% and 33%,respectively;the risetime and the falltime of the strained-channel CMOS are greatly decreased by 50% and 25.47% compared to their traditional Si channel counterparts.The simulation results show that the vertical double-gate（DG） dual-strained-channel MOSFETs exhibit better drive capability,a higher transconductance,and a faster circuit speed for CMOS compared to conventional-Si MOSFETs.The new structure can be achieved by today＇s semiconductor manufacturing level.
A novel device structure with a vertical double-gate and dual-strained channel is presented.The electrical characteristics of this device with a gate length of 100 nm are simulated.With a Ge content of 20%,the drain currents of the strained-Si NMOSFET and the strained-SiGe PMOSFET compared to the universal SOI MOSFETs are enhanced by 26% and 33%,respectively;the risetime and the falltime of the strained-channel CMOS are greatly decreased by 50% and 25.47% compared to their traditional Si channel counterparts.The simulation results show that the vertical double-gate（DG） dual-strained-channel MOSFETs exhibit better drive capability,a higher transconductance,and a faster circuit speed for CMOS compared to conventional-Si MOSFETs.The new structure can be achieved by today＇s semiconductor manufacturing level.
基金
supported by the (Xi’an) Innovation Foundation for Applied Materials of USA (No.XA-AM-2008070)
the Education Bureau of Shannxi Province (No. 08JK384)
