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Adaptive digital calibration techniques for narrow band low-IF receivers with on-chip PLL

Adaptive digital calibration techniques for narrow band low-IF receivers with on-chip PLL
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摘要 Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signal-to-noise ratio and bit error rate,consists of a digitally controlled,high resolution dB-linear automatic gain control(AGC),an inphase(I) and quadrature(Q) gain and phase mismatch calibration,and an automatic frequency calibration(AFC) of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer.The calibration system has a low design complexity with little power and small die area.Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB,respectively,which means the image rejection ratio is better than 60 dB.In addition,the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz. Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signal-to-noise ratio and bit error rate,consists of a digitally controlled,high resolution dB-linear automatic gain control(AGC),an inphase(I) and quadrature(Q) gain and phase mismatch calibration,and an automatic frequency calibration(AFC) of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer.The calibration system has a low design complexity with little power and small die area.Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB,respectively,which means the image rejection ratio is better than 60 dB.In addition,the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第6期100-106,共7页 半导体学报(英文版)
关键词 short range device AGC AFC RECEIVER I/Q calibration short range device AGC AFC receiver I/Q calibration
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参考文献13

  • 1Sheng S, Lynn L, Peroulas J, et al. A low-power CMOS chipset for spread-spectrum communications. Proc ISSCC, San Francisco, 1996:346
  • 2Peiris V, Arm C, Bories C, et al, A 1 V 433/868 MHz 25 kb/s-FSK 2 kb/s-OOK RF transceiver SoC in standard digital 0.18 μm CMOS. IEEE International Solid-States Circuits Conference, 2005
  • 3Jung Y, Jeong H, Song E, et al. A 2.4-GHz 0.25-μm CMOS dual-mode direct-conversion transceiver for Bluetooth and 802.11b. IEEE J Solid-State Circuit, 2004, 39(7): 1185
  • 4Yao Jinke, Chi Baoyong, Wang Zhihua. A novel low power ASK receiver with AGC loop. Chinese Journal of Semiconductors, 2007, 28(3): 337
  • 5Jimenez V P G, Garcia M J F G, Serrano F J G, et al. Design and implementation of synchronization and AGC for OFDM-based WLAN receivers. IEEE Trans Consum Electron, 2004, 50(4): 1016
  • 6Der L, Razavi B. A 2 GHz CMOS image-reject receiver with sign-sign LMS calibration. IEEE Int Solid-State Circuits Conf, Dig Tech Papers, 2001:294
  • 7Montemayor R, Razavi B. A self-calibrating 900 MHz CMOS image-reject receiver. Proc ESSCIRC, 2001:294
  • 8Yu L, Snelgrove W M. A novel adaptive mismatch cancellation system for quadrature IF radio receivers. IEEE Trans CAS - Ⅱ: Analog and Digital Signal Processing, 1999, 46:789
  • 9Li Juan, Zhao Feng, Ye Guojing, et al. A 434/868 MHz CMOS low-IF receiver with I/Q imbalance calibration for SRDs application. Journal of Semiconductors, 2009, 30(3): 035003
  • 10Lyons R G. Understanding digital signal processing. MA: Addison Wesely, 1997

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