摘要
针对FPGA中包含三级可编程开关的互连网络测试,该文提出了一种基于匹配理论的减少配置次数并且与阵列规模无关的测试方法。该方法通过建立结构测试图,按照图的道路长进行分块并应用最小覆盖和最大匹配的原理减少配置次数。对于不同的互连网络结构,与其它方法相比,该方法的配置次数至少减少了10%,并且与阵列规模无关。
Aimed to testing interconnect network that includes 3-stage programmable switches in FPGA, this paper proposes a novel size-independent approach based on a matching theory to minimize the number of test configurations. By constructing the graph of structure test, this paper presents a slicing scheme based on the path pace of the graph, and a method that applies the minimum coverage and maximum matching principle from the graph theory to obtain the minimum number of test configurations. For different interconnect network structure, the number of test configurations in the proposed method is reduced by at least 10% compared with other methods.
出处
《电子与信息学报》
EI
CSCD
北大核心
2009年第6期1479-1482,共4页
Journal of Electronics & Information Technology
关键词
FPGA
互连网络
匹配理论
测试配置次数
FPGA
Interconnect network
Matching theory
Number of test configurations