FPGA片上时钟发生器快速自校准方案

Scheme of Fast Self-Calibration for a FPGA Chip Clock Generator

该文提出了一种新颖的基于频率-电压转换技术的锁相环(PLL)快速自校准方案,可用于FPGA片上时钟产生单元内使用多段调谐环形压控振荡器(VCO)的锁相环。文章详细讨论了校准电路及用作时钟发生器的锁相环关键模块的设计,并进行了整体仿真验证。仿真结果说明,系统能够在发生工艺偏差或者参考频率变化时进行快速自校准。该文设计的校准电路及时钟发生器以较低VCO增益获得较宽的频率调谐范围,并具有较快的锁定时间,适于在FPGA器件的片上时钟产生单元中应用。

This paper presents a novel PLL self-calibration scheme based on Frequency-to-Voltage （F2V） Converting technique, which is fast and applicable for the Phase-Locked Loop（PLL） using a multi-band ring Voltage Controlled Oscillator （VCO） in the clock generation module of a FPGA device. Designs of key modules in the self-calibration circuit are detailed, and simulation of the full system is performed. Simulation results indicate that the system can self-calibrate quickly and properly in case of process variation or reference frequency switch. The clock generator using the proposed self-calibration circuit can obtain a wide frequency operating range while maintaining a relatively low VCO gain and it locks fast, as make it suitable for FPGA clock generation.