AES中字节代换和列混合的硬件可逆设计

Reversible Hardware Designs of ByteSub and MixColumn in AES

针对AES硬件实现占用大量资源的缺点,对其两个核心计算部件(字节代换和列混合)进行了硬件可逆设计。该设计采用模块复用技术,使字节代换及其逆变换模块最大限度地共享GF(28)域中的模逆运算单元,而使列混合及其逆变换模块最大限度地共享p(x)乘运算单元,以较小的硬件代价实现了字节代换模块和列混合模块的硬件可逆设计。最后在Xilinx的FPGA VirtexE xcv2000e-6上进行了仿真验证,实验结果表明,与其他同类设计相比,新设计方案明显减少了硬件开销。

To solve the problem of high resource cost, which exits in implementation of AES, reversible hardware designs of two core parts （ByteSub and MixColumn） are presented in this paper. Utilizing the way of module reuse, pubic operational unit of module inverse in the GF（28） filed is shared by Byte, Sub and its inverse transformation, while pubic operational unit of multiplied p（x ） is shared by MixColumn and its inverse transformation furthest. Area efficient reversible hardware designs of ByteSub and MixCohtmn are implemented. Finally, the proposed architectures are implemented on the VirtexE xcv2000e - 6 apparatus of Xilinx and the simulation results are provided. The results show its efficiency on saving hardware resource occupied comparing with other current designs.