SHA-1算法的HDL设计与仿真

HDL Design and Simulation of SHA-1 Algorithm

随着宽带网络和数字视频的飞速发展,如何加强对数据内容的保护成为迫切需要解决的问题。HDCP是一种目前最有效的版权保护协议,它正是采用了SHA-1算法来验证信息传输的完整性。基于HDL语言的硬件设计方法,可以方便地设计硬件电路,建立SHA-1的算法模型,包括码流填充过程和压缩计算过程。用Verilog HDL描述的电路,其综合结果可通过仿真验证。采用电路结构设计的SHA-1功能模块,简洁高效,可方便地在可编程逻辑器件中实现,并且已在多个嵌入式系统的设计中得到了应用和验证。

The application of wide - bandwidth and digital video is increasing rapidly, it needs to imminently sovle the problem of how to enhance the content protection. HDCP is one of the most efficient wide - bandwidth content protection protocols, which uses SHA - 1 to verify the data integrity of transmission. This paper provided a hardware architecture and implementation of SHA - 1 based on HDL language, established a SHA - 1 algorithm model including symbol stream filling process and compression computational process. The synthesis result of circuit based on Verilong HDL has been verified by simulation. Using this architecture and HDL language, the hardware circuit of SHA - 1 can be designed simply and efficiently. Further more, it is easily to be implemented with FPGA and already applied to many embedded systems.