基于FPGA的循环冗余校验并行实现

Implementation of parallel CRC based on FPGA

在数据通信中为了降低通信线路传输的误码率,需要采用高效能的差错控制方法。循环冗余校验(CRC)由于其误码检测能力强,抗干扰性能优异,在通信和测控等领域有广泛的应用。通过对CRC校验码原理的分析,研究了一种并行CRC算法并采用硬件描述语言Verilog HDL来实现。

In data communications, a high efficient error control method is needed to decrease the rate of error codes. Cyclic Redundancy Check （CRC） is widely used in data communications and measurement ＆ control fields as a powerful method for dealing with data errors. This paper analyzed the principle of CRC, studied a parallel CRC algorithm and implemented it by Verilog HDL.