期刊文献+

基于MAF模型的串扰时延故障的测试矢量生成 被引量:3

Test pattern generation for crosstalk-induced delay faults based on MAF model
下载PDF
导出
摘要 随着深亚微米技术,串扰噪声问题越来越严重。利用MAF模型的基本思想,探讨了一种串扰时延最大化算法,并且利用被修改的FAN算法,生成测试矢量。对于一条敏化通路,利用被修改的FAN算法适当地激活相应的攻击线和受害线,使电路在最恶劣情况下引起最大通路时延,从而实现更有效的时延测试。在标准电路ISCAS’85上进行实验验证,结果表明:该算法对于多攻击线的串扰时延故障的测试矢量产生是有效的。 With deep submieron technology,crosstalk noise becomes more and more serious.This paper uses the theory of Maximal Aggressor Fault model(MAF),and discusses a erosstalk delay maximization algorithm,and generates test vectors by using revised FAN algorithm.For a sensitization path,the con'esponding aggressors and victim are activated appropriately by using revised FAN algorithm,so that the circuit in the worst case has induced the greatest path delay,and more effective delay test is achieved.By assessing on ISCAS'85 benchmark circuits,experimental results show that the algorithm is effective for crosstalkinduced delay faults by multiple aggressors.
出处 《计算机工程与应用》 CSCD 北大核心 2009年第19期62-65,共4页 Computer Engineering and Applications
基金 国家部委预研项目
关键词 时延故障 多攻击线 最大攻击线故障模型 测试矢量生成 FAN算法 delay fault multiple aggressors Maximal Aggressor Fault (MAF) model test pattern generation FAN algorithm
  • 相关文献

参考文献9

  • 1Nordho I P,Treytanar D,Otterstedt J.Signal integrity problems in deep submicron arising from interconnects between cores[C]//Proceedings 16th IEEE VLSI Test Symposium, 1998:28-33.
  • 2张月,李华伟,宫云战,李晓维.针对串扰引起的时延故障的测试产生[J].计算机辅助设计与图形学学报,2004,16(10):1448-1453. 被引量:2
  • 3Tek L K,Nordquist C,Abraham J A.Automatic test pattern generation for crosstalk glitches in digital circuits[C]//Proceedings 16th IEEE VLSI Test Symposium, 1995:34-39.
  • 4Weiyu C,Gupta S K,Breuer M A.Test generation in VLSI circuits for crosstalk noise[C]//Proceedings International Test Conference, 1998 : 641-650.
  • 5Krstic A,Jing-Jia L,Yi-Min J,et al.Delay testing considering crosstalk-induce effects[C]//Proceedings International Test Conference,2001:558-567.
  • 6Satyendra R.Crosstalk delay analysis in very deep sub-micron VLSI circuits[D].USA:Southern Mehodist University,2004.
  • 7Cuviello M,Dey S,Bai X.Fauh modeling and simulation for crosstalk in system-on-chip interconnect[C]//1999IEEE/ACM international Conference on Computer-Aided Design,1999:297-303.
  • 8Aniket,Arunachalam R.A novel algorithm for testing erosstalk induce delay faults in VLSI circuits[C]//The 18th International Conference on VLSI Design,2005:479-484.
  • 9Chen W Y,Gupta S K,Bruer M A.Test generation for crosstalkinduced faults:Framework and computational resuhs[C]//Proceedings of the 9th Asian Test Symposium,2000 : 305-310.

二级参考文献7

  • 1闵应骅,李忠诚,赵著行.Boole过程论[J].中国科学(E辑),1996,26(6):541-548. 被引量:13
  • 2Chen W Y, Gupta S K, Breuer M A. Test generation for crosstalk-induced delay in integrated circuits[A]. In: Proceedings of IEEE International Test Conference, Atlantic City, 1999. 191~200
  • 3Krstic A, et al. Delay testing considering crosstalk-induced effects[A]. In: Proceedings of IEEE International Test Conference, Baltimore, 2001. 558~567
  • 4Cheng K T, Chen H C. Classification and identification of nonrobust untestable path delay faults[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and System, 1996, 15(8): 845~853
  • 5Li H, Li Z, Min Y. Delay testing with double observations[A]. In: Proceedings of the 7th Asian Test Symposium, Singapore, 1998. 96~100
  • 6Chen W Y, Gupta S K, Bruer M A. Test generation for crosstalk-induced faults: Framework and computational results[A]. In: Proceedings of the 9th Asian Test Symposium, Taipei, 2000. 305~310
  • 7Li Z, Min Y, Brayton R K. Efficient identification of non-robustly untestable path delay faults[A]. In: Proceedings of IEEE International Test Conference, Washington D C, 1997. 992~997

共引文献1

同被引文献11

引证文献3

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部