多电源混合电压SoC的全芯片ESD设计实例

The Whole-chip ESD Design for Multi-power and Mixed-voltage SoC

SoC是含有微处理器、外围电路等的超大规模集成电路,具有器件特征尺寸小、复杂度高、面积大、数模混合等特点,SoC的ESD设计成为设计师面临的一个新的设计挑战。文章详细介绍了一个复杂的多电源、混合电压专用SoC芯片的全芯片ESD设计方案,并结合电路特点仔细分析了SoC芯片ESD设计的难点,提出了先工艺、再器件、再电路三个层次的分析思路,并将芯片ESD总体解决方案中的关键设计重点进行了逐一分析,最后给出了全芯片ESD防护架构的示意图。该SoC芯片基于0.35μ m2P4M Polycide混合信号CMOS工艺流片,采用文中提出的全芯片ESD防护架构,使该芯片的HBM ESD等级达到了4kV。

SoC is a VLSI with microprocessor, peripheral circuits, and so o.n. SoC has some special features such as small device feature size, unusual complexity, large chip size and mixed-signals, etc.. All this leads chip designer to a new challenge in SoC ESD design. A whole-chip ESD protection solution of complicated multipower, mixed-voltage, application-specified SoC is proposed in this paper. Considering the chip specialties, detailed analyses for the ESD design difficulties of SoC are proposed in the paper. An analysis idea of＂process first, device then, circuit last＂ for ESD design is provided. Detail analyses for design keys of ESD total solution are proposed one by one too. A whole-chip ESD protection composition of a picture is provided in the end. Based on 0.35 μm 2P4M Polvcide mixed-signal CMOS process, its HBM ESD level reaches 4kV by using the proposed whole-chip ESD protection plan.