基于Wishbone片上总线的IP核的互联

Interconnection between IP Cores Based on Wishbone Bus

以FPGA技术为基础,以Verilog HDL为载体,设计了遵守Wishbone片上总线规范的IP核接口,实现了片上系统的IP核互联。

According to Wishbone bus protocol, IP cores interfaces based on FPGA and Verilog HDL have been designed. They can be used to connect IP cores on SOC.