IS95/cdma2000授时提取模块的设计

The design of timing abstraction from IS95/cdma2000 systems

设计了一种IS95/CDMA2000授时模块,以零中频接收芯片SA9521为核心将射频信号解调到I/Q基带,采用Xilinx公司的Spartan-3A DSP系列FPGA XC3SD1800A进行基带处理,通过接收IS95/CDMA2000前向链路中的导频信道和同步信道,输出高精度秒脉冲和本地时间,秒脉冲精度优于1微秒。

A IS95/CDMA2000 timing abstraction module is designed, which shifts radio signal to the I/O baseband through A9521 CMOS chip in Zero-IF architecture. The baseband processes are implemented in Xilinx＇s Spatran-3A DSP FPGA Family-XC3SD1800A. By receiving the PILOT Channel and SYNC Channel in forward link, this module can output second pulses with high precision which is better than 1μs.