摘要
Array-LDPC码是一种高码率的LDPC(低密度奇偶校验)码,具有高性能、易编码等特点,广泛应用于DSL(数字用户线)传输中。在分析Array LDPC码结构和MS(最小和)算法的基础上,提出一种在较低硬件复杂度下实现较高并行度的解码器架构。该架构显著降低了节点间的信息通信量,同时,用局部CPU之间有规律的信息传递取代了VPU与CPU之间复杂的信息交换,解决了硬件实现中的布线问题。设计结果表明,采用这种架构设计的(2209,2021)Array-LDPC解码器具有吞吐率高、结构简单的优点,在0.18μm CMOS工艺下,面积仅为2.4 mm2,而吞吐率可达到1.03 Gbps。
Array-LDPC code is a kind of low-density parity-check （LDPC） codes, having characteristics of high performance, easy coding etc.. Therefore, the Array-LDPC codes are extensively applied in the digital subscriber-line （DSL） transmission systems. From the analysis of Array LDPC code structure and the MS （Min-Sum） algorithm, this paper presents a decoding structure of Array LDPC with high parallel degree and low circuit complexity. That structure reduced the communication quantity of the nodes significantly. In the meantime, regular information transmission between local CPUs is used to replace complex VPU and CPU in- formation exchange, thus resolving problem of hardware layout. Design result shows that the decoder using this structure has the advantages of high throughput and simple structure. In fact, the （2209,2021） Array-LDPC decoder is designed using this structure, its throughput is 1.03Gbps and its area is only 2.4 by 0.18μm CMOS technology.
出处
《信息化研究》
2009年第6期29-32,共4页
INFORMATIZATION RESEARCH
关键词
LDPC码结构
最小和算法
并行度
LDPC code structure
Min-Sum algorithm
parallel degree
