继电保护专用芯片存储器抗干扰性研究与设计

Study and Design of Anti-interference for on-chip Memory in Relay Protective Application Specific Chip

目前依赖于外置存储器的继电保护装置容易受到现场复杂电磁环境的干扰而影响系统的正常运行,采用片内存储器层次结构设计的专用芯片可有效地降低电磁干扰对数据读写影响程度.从片内FIFO性能分析、嵌入式DRAM的实现工艺、片内SDRAM控制器的抗干扰设计等方面说明了提高片内存储器可靠性的方法和原理.结果显示该方法能够显著地提高芯片的抗干扰能力,从而提高了不依赖于外置存储器的继电保护装置的可靠性.

Up to now, the relay protective equipments using off-chip memory devices were easily interfered in extremely complex electromagnetic environment. The approach of on-chip memory hierarchy was adopted in design of an application specific chip. It can efficiently decrease the dectromagnetic interference＇s influence in data operating. The methods to enhance reliability of on-chip memory are detailed in terms of analysis of on-chip FIFO, implemented technics of embedded DRAM, and anti-interference technologies of SDRAM controller. The results show that it can improve anti-interference＇s ability of specific chips; furthermore, it also enhances the reliabilities of relay protective equipment with off-chip memory.