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同步数据触发体系结构中指令预取技术研究

Research on the Instruction Prefetching Technology for the Synchronous Data Triggered Architecture
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摘要 同步数据触发体系结构SDTA将传统指令级并行细化到微操作级并行,具有较高的数据处理能力,但其特殊的指令格式及指令特性,给指令Cache访问带来了挑战。指令预取技术能够有效地降低指令Cache的访问失效率,增强处理器取指能力,提高性能。本文分析了SDTA指令集特性,提出了一种适合SDTA指令集特性的软硬件相结合的混合指令预取机制,采用硬件预取引擎和软件提示相结合进行预取。该方法能够有效地提高指令Cache命中率,且具有实现简单、无效预取率低、不会增加代码体积等特点。 The synchronous data triggered architecture provides parallelism from the instruction level to the micro-operation level and is powerful in data processing while its special instruction property raises challenge to the instruction cache access. The instruction prefetching technology can reduce the miss rate of the instruction cache, enhance the instruction fetch ability, and improve the processor performance. Based on the analysis of the SDTA instruction set＇s characteristics, a hybrid instruction prefetching mechanism is proposed, which can increase the hit rate of the instruction cache. The proposed software/hardware-integrated mechanism has the following advantages： easy implementation, fewer invalid prefetches and no increase on the program code size, etc.
作者 郭建军 戴葵 王志英
机构地区 国防科技大学计算机学院
出处 《计算机工程与科学》 CSCD 北大核心 2009年第8期77-81,共5页 Computer Engineering & Science
基金 国家自然科学基金资助项目(60773024) 国家973计划资助项目(2007CB310901)
关键词 同步数据触发体系结构 指令预取 微操作级并行 SDTA instruction prefetch micro-operation level parallelism
分类号 TP303 [自动化与计算机技术—计算机系统结构]
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参考文献20

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计算机工程与科学
2009年 第8期

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