UWB中Viterbi译码器的FPGA设计与实现

Design and Implementation of Viterbi Decoder Based on FPGA for UWB

由于差错控制在超宽带室内导航系统中占据着十分重要的位置,并考虑到IEEE802.15.3a标准采用卷积编码和Viterbi译码来进行差错控制,因此利用现场可编程门阵列(FPGA)设计实现了一种约束长度为7,译码深度为64的全并行Viterbi译码器。本设计在Xilinx ISE9.2环境下进行了综合,并采用Modelsim6.0对整个设计进行了仿真。仿真结果表明,该设计能够满足超宽带系统的要求。

Since it is very important to lower the error rate of the transition data in indoor navigation systems based on UWB technology, and a convolution encoder and a Viterbi decoder in channel coding are employed to control the error rate in the IEEE 802.15.3a protocol, a parallel Viterbi decoder has been designed and implemented, for which a constraint length of 7 and a trace back depth of 64 have been achieved. The design has been synthesized in Xilinx ISE 9.2 and simulated in Modelsim 6.0. The simulation results indicate that the design can match the request of the UW-B system.