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锁相环相位噪声与环路带宽的关系分析 被引量:9

Relationship Analysis between PLL Phase Noise and PLL Bandwidth
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摘要 应用电荷泵锁相环系统的等效噪声模型,分析电荷泵锁相环相位噪声在不同频率段的功率谱密度。据此得到相位噪声的功率谱密度与频率关系的模拟曲线。分析与模拟的结论指出环路噪声具有低通特性,而VCO噪声在低频区衰减明显,在设计锁相环路时需要综合考虑环路和VCO两种噪声的影响,然后才能确定环路带宽。该结论对于电荷泵锁相环的相位噪声与环路带宽设计具有一定的参考意义。 This paper analyzes the power spectrum density of different frequencies on charge- pump PLL phase noise by applying PLL system equivalent noise model,which has gained the simulation curve of the relationship between the phase noise power spectral density and the frequency. The conclusion points out that loop noise has low passing feature and VCO noise obviously declines in low frequency,and considers both loop noise and VCO noise when designing PLL, then PLL bandwidth can be defined. That conclusion has a certain reference sense for charge - pump PLL phase noise and loop bandwidth design.
出处 《现代电子技术》 2009年第14期132-134,共3页 Modern Electronics Technique
基金 湖南省教育厅资助科研项目
关键词 电荷泵锁相环 相位噪声 功率谱密度 环路带宽 charge - pump PLL phase noise power spectrum density PLL bandwidth
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  • 1王洪魁,袁小云,张瑞智.三阶电荷泵锁相环事件驱动模型的新算法[J].固体电子学研究与进展,2004,24(4):482-485. 被引量:1
  • 2肖高标,吴杰.无源RC电流滤波器综合与设计[J].湖南大学学报(自然科学版),1995,22(4):86-90. 被引量:1
  • 3Razavi B.RF Microelectronics[M].USA:Prentice Hall PTR,1998,270-277.
  • 4KeliuShu.A 2.4-GHz Monolithic Fractional-N Frequency Synthesizer with Robust Phase-Switching Prescaler and Loop Capacitance Multiplier[J].IEEE Journal of Solid-State Circuits,June 2003,38(6):866-874.
  • 5Sam Yinshang Sun.An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance[J].IEEE Journal of Solid-State Circuits,April 1989,SC-24,325-330.
  • 6Adrian Maxim.A 2-5GHz Low Jitter 0.13μm CMOS PLL Using a Dynamic Current Matching Charge-Pump and a Noise Attenuating Loop-Filter[C].In:IEEE 2004 Custom Integrated Circuits Conference:147-150.
  • 7Floydm.Gardner.Phaselock Techniques[M].USA:A Wiley-Interscience Publication,1979,second edition,9-24.
  • 8Floydm.Gardner.Charge-Pump Phase-Lock Loops[J].IEEE Transactions on Communications,November 1980,COM-28(11):1849-1858.
  • 9Hung Chih-Ming.A Fully Integrated 1.5-V 5.5-GHz CMOS Phase-Locked Loop[J].IEEE Journal of Solid-State Circuits,April 2002,37(4):521-525.
  • 10Rategh H R,Samavati H and Lee T H.A 5-GHz 32-mW CMOS Frequency Synthesizer with anInjection Locked Frequency Divider[C].In:Proc.IEEE Symp VLSI Circuits,June 1999:113-116.

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